The present invention relates generally to static random-access memory (SRAM) semiconductor devices, and more particularly, to a method of forming a low current fin field effect transistor (FinFET) structure to improve circuit density of an SRAM device.
SRAM cell design typically begins by selecting the smallest p-type field effect transistor (PFET) supported by a particular technology and then scaling the n-type field effect transistor (NFET) pass gate and pull-up, p-type field effect transistors (PU PFETs) accordingly for proper current drive ratio. Balancing the drive current ratio results in optimizing the read/write operation of the SRAM device. With the recent improvements in PFET device performance (e.g., increased hole mobility through the silicon <110> PFET channels), the recent introduction of increasing amounts of uniaxial strain to PFET devices (both through over-layer stress liner films and embedded silicon germanium (SiGe) source/drains), PFET devices typically provide a higher drive current than the drive current provided by NFET devices. This drive current differential degrades writeability signal to noise margins in existing SRAM designs because the NFET pass-gates are now relatively weaker when operating against the PFET and PU PFET during a write event.
SRAM devices typically implement one or more PFETs (i.e., SRAM PFETs) in the SRAM cell itself, and also one or PFETs (i.e., logic PFETs) in the logic portion. Both the SRAM PFETs and logic PFETs share the same structure, making their performance comparable when corrected for threshold voltage. Conventional methods have addressed the drive current differential by forming the pass gate with multiple fins. Other methods for addressing the drive current differential include implementing additional FET devices (e.g., keeper FETs) connected to the NFET array. Each of these methods control the current drive ratio, but at the cost of diminishing the overall circuit density of the SRAM device.